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ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
13 years 11 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
INTEGRATION
2008
96views more  INTEGRATION 2008»
13 years 7 months ago
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
ISLPED
2003
ACM
129views Hardware» more  ISLPED 2003»
14 years 18 days ago
A critical analysis of application-adaptive multiple clock processors
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
Emil Talpes, Diana Marculescu
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 19 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ICNP
2009
IEEE
14 years 2 months ago
Accurate Clock Synchronization for IEEE 802.11-Based Multi-Hop Wireless Networks
—Clock synchronization is an essential building block for many control mechanisms used in wireless networks, including frequency hopping, power management, and packet scheduling....
Jui-Hao Chiang, Tzi-cker Chiueh