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HPDC
2010
IEEE
13 years 7 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
CODES
2007
IEEE
14 years 1 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
IPPS
2008
IEEE
14 years 2 months ago
A Hybrid MPI design using SCTP and iWARP
Abstract— Remote Direct Memory Access (RDMA) and pointto-point network fabrics both have their own advantages. MPI middleware implementations typically use one or the other, howe...
Mike Tsai, Brad Penoff, Alan Wagner
CODES
2003
IEEE
14 years 27 days ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
EUROMICRO
2006
IEEE
14 years 1 months ago
Visualization of Areas of Interest in Component-Based System Architectures
Understanding complex component-based systems often requires getting insight in how certain system properties, such as performance, trust, reliability, or structural attributes, c...
Heorhiy Byelas, Egor Bondarev, Alexandru Telea