5658 search results - page 1106 / 1132 » An Efficient Counting Network |
ISMVL
1997
IEEE
14 years 26 days ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
RTAS
1997
IEEE
14 years 26 days ago
1997
IEEE
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
ISCA
1996
IEEE
14 years 24 days ago
1996
IEEE
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
ICCAD
1994
IEEE
14 years 23 days ago
1994
IEEE
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
ICALP
1993
Springer
14 years 22 days ago
1993
Springer
The divide-and-conquer principle is a majoi paradigm of algorithms design. Corresponding cost functions satisfy recurrences that directly reflect the decomposition mechanism used i...