Sciweavers

62 search results - page 10 / 13
» An Efficient Fault-Tolerant VLSI Architecture Using Parallel...
Sort
View
CIKM
2009
Springer
14 years 10 hour ago
Density-based clustering using graphics processors
During the last few years, GPUs have evolved from simple devices for the display signal preparation into powerful coprocessors that do not only support typical computer graphics t...
Christian Böhm, Robert Noll, Claudia Plant, B...
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
14 years 7 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
CODES
2004
IEEE
13 years 11 months ago
Design and programming of embedded multiprocessors: an interface-centric approach
We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developin...
Pieter van der Wolf, Erwin A. de Kock, Tomas Henri...
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 1 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
14 years 1 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper