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ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
14 years 5 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek
FPT
2005
IEEE
132views Hardware» more  FPT 2005»
14 years 4 months ago
Implementation of Gabor-Type Filters on Field Programmable Gate Arrays
Although biological visual systems have been widely studied at the physiological, psychophysical and functional levels, our understanding of its signal processing mechanisms is st...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....
MSS
2003
IEEE
113views Hardware» more  MSS 2003»
14 years 4 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong
IJNSEC
2008
166views more  IJNSEC 2008»
13 years 11 months ago
Countermeasures for Hardware Fault Attack in Multi-Prime RSA Cryptosystems
The study of countermeasures for hardware fault attack in multi-prime RSA cryptosystems is very important for applications such as computer network and smart cards. In this paper,...
Zine-Eddine Abid, Wei Wang
ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
14 years 3 months ago
Stereo Correspondence with Discrete-Time Cellular Neural Networks
In this paper, we propose a new approach of solving the stereopsis problem with a discrete-time cellular neural network(DTCNN) where each node has connectionsonly with its local n...
Sungjun Park, Seung-Jai Min, Soo-Ik Chae