Sciweavers

286 search results - page 42 / 58
» An Efficient Hardware Implementation of Feed-Forward Neural ...
Sort
View
ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 9 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
14 years 4 months ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ARC
2010
Springer
126views Hardware» more  ARC 2010»
13 years 9 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
ARCS
2007
Springer
14 years 5 months ago
Architecture for Collaborative Business Items
Sensor network technology is pushing towards integration into the business world. By using sensor node hardware to augment real life business items it is possible to capture the wo...
Till Riedel, Christian Decker, Phillip Scholl, Alb...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
14 years 2 months ago
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currentl...
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha