Sciweavers

697 search results - page 92 / 140
» An Efficient Hardware Support for Control Data Validation
Sort
View
CC
2007
Springer
14 years 3 months ago
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung...
JPDC
2006
111views more  JPDC 2006»
13 years 9 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
SIGCOMM
2010
ACM
13 years 9 months ago
Scalable flow-based networking with DIFANE
Ideally, enterprise administrators could specify fine-grain policies that drive how the underlying switches forward, drop, and measure traffic. However, existing techniques for fl...
Minlan Yu, Jennifer Rexford, Michael J. Freedman, ...
CODES
2005
IEEE
14 years 2 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 16 days ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...