3 search results - page 1 / 1 » An Efficient Hierarchical Timing-Driven Steiner Tree Algorit... |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
TCAD
2002
13 years 7 months ago
2002
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
GLVLSI
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...