113 search results - page 11 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
ESA
2009
Springer
14 years 2 months ago
2009
Springer
Finding sparse cuts is an important tool for analyzing large graphs that arise in practice, such as the web graph, online social communities, and VLSI circuits. When dealing with s...
FCCM
2009
IEEE
13 years 11 months ago
2009
IEEE
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
INTEGRATION
2007
13 years 7 months ago
2007
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...
ISPD
2003
ACM
14 years 20 days ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...