113 search results - page 4 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
PDP
2003
IEEE
14 years 20 days ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
EURODAC
1990
IEEE
13 years 11 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...