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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 11 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
ASAP
2004
IEEE
141views Hardware» more  ASAP 2004»
13 years 11 months ago
Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields
Binary finite fields GF(2n ) are very commonly used in cryptography, particularly in publickey algorithms such as Elliptic Curve Cryptography (ECC). On word-oriented programmable ...
A. Murat Fiskiran, Ruby B. Lee
PPOPP
2003
ACM
14 years 22 days ago
Improving server software support for simultaneous multithreaded processors
Simultaneous multithreading (SMT) represents a fundamental shift in processor capability. SMT's ability to execute multiple threads simultaneously within a single CPU offers ...
Luke McDowell, Susan J. Eggers, Steven D. Gribble
LCPC
2001
Springer
13 years 12 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann