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» An Evaluation of Directory Schemes for Cache Coherence
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ASPLOS
1991
ACM
13 years 11 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
ISCA
1998
IEEE
123views Hardware» more  ISCA 1998»
13 years 11 months ago
An Evaluation of Directory Schemes for Cache Coherence
Anant Agarwal, Richard Simoni, John L. Hennessy, M...
ICPP
1990
IEEE
13 years 11 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
IPPS
1999
IEEE
13 years 11 months ago
Segment Directory Enhancing the Limited Directory Cache Coherence Schemes
We present a new arrangement of directory bits called the segment directory to improve directory storage efficiency: a segment directory can point to several sharing processors wi...
Jong Hyuk Choi, Kyu Ho Park
ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
13 years 11 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan