34 search results - page 7 / 7 » An Evaluation of Directory Schemes for Cache Coherence |
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
A particularly insidious type of concurrency bug is atomicity violations. While there has been substantial work on automatic detection of atomicity violations, each existing techn...