A scalable approach to thread-level speculation

While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performancepotential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry
• Keywords: Cost-effective Parallel Machines, Hardware, ISCA 2000, Machine Size, Threads Despite Uncertainty