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EUROGP
2001
Springer
124views Optimization» more  EUROGP 2001»
15 years 7 months ago
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
Massimiliano Erba, Roberto Rossi, Valentino Libera...
125
Voted
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
15 years 8 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
SAMOS
2005
Springer
15 years 8 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
16 years 3 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
134
Voted
ISSTA
2004
ACM
15 years 8 months ago
Evolutionary testing in the presence of loop-assigned flags: a testability transformation approach
Evolutionary testing is an effective technique for automatically generating good quality test data. However, for structural testing, the technique degenerates to random testing i...
André Baresel, David Binkley, Mark Harman, ...