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TOMACS
1998
140views more  TOMACS 1998»
15 years 4 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
TCAD
2002
104views more  TCAD 2002»
15 years 4 months ago
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
TVLSI
2002
97views more  TVLSI 2002»
15 years 4 months ago
Techniques for energy-efficient communication pipeline design
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
Gang Qu, Miodrag Potkonjak
VLSISP
2002
112views more  VLSISP 2002»
15 years 4 months ago
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dat...
Ramaswamy Govindarajan, Guang R. Gao, Palash Desai
DBKDA
2010
IEEE
127views Database» more  DBKDA 2010»
15 years 3 months ago
Failure-Tolerant Transaction Routing at Large Scale
—Emerging Web2.0 applications such as virtual worlds or social networking websites strongly differ from usual OLTP applications. First, the transactions are encapsulated in an AP...
Idrissa Sarr, Hubert Naacke, Stéphane Gan&c...
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