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» An Experimental Chip to Evaluate Test Techniques: Chip and E...
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DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 1 months ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
BMCBI
2006
90views more  BMCBI 2006»
13 years 7 months ago
The PowerAtlas: a power and sample size atlas for microarray experimental design and research
Background: Microarrays permit biologists to simultaneously measure the mRNA abundance of thousands of genes. An important issue facing investigators planning microarray experimen...
Grier P. Page, Jode W. Edwards, Gary L. Gadbury, P...
PPOPP
2009
ACM
14 years 7 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...
ETS
2007
IEEE
81views Hardware» more  ETS 2007»
14 years 1 months ago
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Dependability is an important attribute for microfluidic biochips that are used for safety-critical applications such as point-of-care health assessment, air-quality monitoring, a...
Tao Xu, Krishnendu Chakrabarty
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
14 years 2 months ago
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu,...