260 search results - page 11 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
AHS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...