260 search results - page 30 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
HOTI
2002
IEEE
14 years 26 days ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
ICDE
2009
IEEE
14 years 9 months ago
2009
IEEE
In recent years, the sketch-based technique has been presented as an effective method for counting stream items on processors with limited storage and processing capabilities, such...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...