260 search results - page 4 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
DATE
2010
IEEE
14 years 3 days ago
2010
IEEE
Abstract—In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may sup...
ISIP
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper proposes an FPGA implementation of an Adaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Sp...
FPGA
2009
ACM
13 years 11 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
INTEGRATION
2007
13 years 6 months ago
2007
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
CASES
2006
ACM
14 years 29 days ago
2006
ACM
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...