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HPCA
2005
IEEE
15 years 11 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 11 months ago
Microarchitecture of a High-Radix Router
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
John Kim, William J. Dally, Brian Towles, Amit K. ...
KCAP
2003
ACM
15 years 11 months ago
Learning programs from traces using version space algebra
While existing learning techniques can be viewed as inducing programs from examples, most research has focused on rather narrow classes of programs, e.g., decision trees or logic ...
Tessa A. Lau, Pedro Domingos, Daniel S. Weld
SENSYS
2003
ACM
15 years 11 months ago
Taming the underlying challenges of reliable multihop routing in sensor networks
The dynamic and lossy nature of wireless communication poses major challenges to reliable, self-organizing multihop networks. These non-ideal characteristics are more problematic ...
Alec Woo, Terence Tong, David E. Culler
163
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ICADL
2003
Springer
117views Education» more  ICADL 2003»
15 years 11 months ago
Metadata++: A Scalable Hierarchical Framework for Digital Libraries
: Metadata++ is a digital library system that we are developing to serve the needs of the United States Department of Agriculture Forest Service, the United States Department of th...
Mathew Weaver, Lois M. L. Delcambre, Timothy Tolle