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HPDC
2008
IEEE
14 years 3 months ago
StoreGPU: exploiting graphics processing units to accelerate distributed storage systems
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...
Samer Al-Kiswany, Abdullah Gharaibeh, Elizeu Santo...
CGO
2004
IEEE
14 years 29 days ago
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to the outer loops. In a companion paper, we proposed a ...
Hongbo Rong, Alban Douillet, Ramaswamy Govindaraja...
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
14 years 2 months ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...
ISCAPDCS
2007
13 years 10 months ago
PARALLEL-TCOFFEE: A parallel multiple sequence aligner
In this paper we present a parallel implementation of T–Coffee — a widely used multiple sequence alignment package. Our software supports a majority of options provided by the...
Jaroslaw Zola, Xiao Yang, Adrian Rospondek, Sriniv...
IBMRD
2006
63views more  IBMRD 2006»
13 years 9 months ago
Decomposing the load-store queue by function for power reduction and scalability
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
Lee Baugh, Craig B. Zilles