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RTSS
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
GLOBECOM
2008
IEEE
13 years 8 months ago
2008
IEEE
Abstract—This paper investigates the zero-forcing (ZF) beamforming transmit strategy in the multiple-antenna multiuser downlink systems. We consider the case of mobile users equi...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
RTAS
2005
IEEE
14 years 1 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...