Sciweavers

347 search results - page 65 / 70
» An Input Output HMM Architecture
Sort
View
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 2 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
14 years 2 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
EMSOFT
2009
Springer
14 years 1 months ago
Handling mixed-criticality in SoC-based real-time embedded systems
System-on-Chip (SoC) is a promising paradigm to implement safety-critical embedded systems, but it poses significant challenges from a design and verification point of view. In ...
Rodolfo Pellizzoni, Patrick O'Neil Meredith, Min-Y...
GECCO
2007
Springer
182views Optimization» more  GECCO 2007»
14 years 1 months ago
Generating large-scale neural networks through discovering geometric regularities
Connectivity patterns in biological brains exhibit many repeating motifs. This repetition mirrors inherent geometric regularities in the physical world. For example, stimuli that ...
Jason Gauci, Kenneth O. Stanley
IPPS
2005
IEEE
14 years 1 months ago
Predicting Cache Space Contention in Utility Computing Servers
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ...
Yan Solihin, Fei Guo, Seongbeom Kim