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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
CODES
2009
IEEE
13 years 11 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
IPPS
2010
IEEE
13 years 5 months ago
Using focused regression for accurate time-constrained scaling of scientific applications
Many large-scale clusters now have hundreds of thousands of processors, and processor counts will be over one million within a few years. Computational scientists must scale their ...
Bradley J. Barnes, Jeonifer Garren, David K. Lowen...
ISQED
2011
IEEE
240views Hardware» more  ISQED 2011»
12 years 10 months ago
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
Oleg Garitselov, Saraju P. Mohanty, Elias Kougiano...
ICCAD
2008
IEEE
172views Hardware» more  ICCAD 2008»
14 years 2 months ago
Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis
— Perturbation Projection Vector (PPV) is an established technique for oscillator phase noise analysis; However, the PPV method significantly loses accuracy when circuits have l...
Xiaolue Lai