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VTS
1996
IEEE
112views Hardware» more  VTS 1996»
14 years 28 days ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
14 years 2 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
CDC
2009
IEEE
126views Control Systems» more  CDC 2009»
14 years 3 days ago
An approach for the state estimation of Takagi-Sugeno models and application to sensor fault diagnosis
— In this paper, a new method to design an observer for nonlinear systems described by Takagi-Sugeno (TS) model, with unmeasurable premise variables, is proposed. Most of existin...
Dalil Ichalal, Benoît Marx, José Rago...
DATE
2004
IEEE
142views Hardware» more  DATE 2004»
14 years 16 days ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
DSN
2004
IEEE
14 years 16 days ago
Optimal Object State Transfer - Recovery Policies for Fault Tolerant Distributed Systems
Recent developments in the field of object-based fault tolerance and the advent of the first OMG FTCORBA compliant middleware raise new requirements for the design process of dist...
Panagiotis Katsaros, Constantine Lazos