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DAC
2004
ACM
14 years 10 months ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
14 years 9 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
CIKM
2009
Springer
14 years 3 months ago
Packing the most onto your cloud
Parallel dataflow programming frameworks such as Map-Reduce are increasingly being used for large scale data analysis on computing clouds. It is therefore becoming important to a...
Ashraf Aboulnaga, Ziyu Wang, Zi Ye Zhang
GLOBECOM
2008
IEEE
14 years 3 months ago
Link Rate Allocation under Bandwidth and Energy Constraints in Sensor Networks
—In sensor networks, both energy and bandwidth are scarce resources. In the past, many energy efficient routing algorithms have been devised in order to maximize network lifetim...
Maggie X. Cheng, Xuan Gong, Lin Cai
WSC
2008
13 years 11 months ago
Maximizing the utilization of operating rooms with stochastic times using simulation
This paper addresses a surgery rooms scheduling problem. The problem is modeled as a parallel machine scheduling problem with sequence dependent setup times and an objective of mi...
Jean-Paul M. Arnaout, Sevag Kulbashian