60 search results - page 3 / 12 » An Issue Logic for Superscalar Microprocessors |
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
DFT
2008
IEEE
13 years 9 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
In this paper we investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are bene ts to using the decoupling para...
PACS
2004
Springer
14 years 22 days ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...