203 search results - page 16 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
RTAS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Software instrumentation is a key technique in many stages of the development process. It is of particular importance for debugging embedded systems. Instrumented programs produ...
TCAD
2008
13 years 7 months ago
2008
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
TCAD
2008
13 years 7 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...