ISLPED 1996 - PDF Preprint Papers

ISLPED 1996 International Symposium on Low Power Electronics and Design

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ISLPED
1996
ACM

143views Hardware» more ISLPED 1996»

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

14 years 4 months ago

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Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Ko...

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Id	Views	Title	Status

1	143	Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer	claim
2	121	A low power high performance switched-current multiplier	claim
3	112	Data driven signal processing: an approach for energy efficient computing	claim
4	110	Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques	claim
5	109	Transition reduction in carry-save adder trees	claim
6	105	Energy delay analysis of partial product reduction methods for parallel multiplier implementation	claim
7	103	A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes	claim
8	102	High-level power estimation and the area complexity of Boolean functions	claim
9	101	High-level power estimation	claim
10	100	Basic experimentation on accuracy of power estimation for CMOS VLSI circuits	claim
11	93	The design of a high performance low power microprocessor	claim
12	93	250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies	claim
13	92	Concurrency-oriented optimization for low-power asynchronous systems	claim
14	91	Energy minimization using multiple supply voltages	claim
15	91	Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models	claim
16	91	Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices	claim
17	89	Low power systems for wireless microsensors	claim
18	89	A novel methodology for transistor-level power estimation	claim
19	83	12-b 125 MSPS CMOS D/A designed for spectral performance	claim
20	82	A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element	claim
21	81	Simulation based architectural power estimation for PLA-based controllers	claim
22	80	Implementation of a micro power 15-bit "floating-point" A/D converter	claim
23	79	Micro power "relative precision" 13 bits cyclic RSD A/D converter	claim
24	79	A low power switching power supply for self-clocked systems	claim
25	78	Gate-level current waveform simulation of CMOS integrated circuits	claim
26	76	Comparison of high speed voltage-scaled conventional and adiabatic circuits	claim
27	74	Gate-level synthesis for low-power using new transformations	claim
28	73	Effects of random MOSFET parameter fluctuations on total power consumption	claim
29	72	Simultaneous buffer and wire sizing for performance and power optimization	claim
30	72	Energy recovery for the design of high-speed, low-power static RAMs	claim
31	71	Floating body effects in partially-depleted SOI CMOS circuits	claim
32	70	Circuit techniques for low-power CMOS GSI	claim
33	69	Substrate noise influence on circuit performance in variable threshold-voltage scheme	claim
34	68	Energy-recovery CMOS for highly pipelined DSP designs	claim
35	65	Short circuit power consumption of glitches	claim
36	65	Lower bounds on power dissipation for DSP algorithms	claim
37	51	Practical performance/power alternatives within an existing CMOS technology generation	claim

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