Simultaneous buffer and wire sizing for performance and power optimization

In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip andHSPICE simulationsshowthat our algorithms canreduceskew and power by a factor of 3

• Type: Conference
• Year: 1996
• Where: ISLPED
• Authors: Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
• Keywords: Clock Nets, Efficient Optimal Algorithm, Hardware, ISLPED 1996, Optimal Sbws Solutions