203 search results - page 9 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
VLSID
2002
IEEE
14 years 9 days ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
ISQED
2002
IEEE
14 years 9 days ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of VLSI circuits. In this paper we focus on one reliabil...
COR
2008
13 years 7 months ago
2008
-- The optimal buffer allocation in queueing network systems is a difficult stochastic, non-linear, integer mathematical programming problem. Moreover, the objective function, the ...