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CODES
2010
IEEE
13 years 4 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...
CODES
2003
IEEE
14 years 28 days ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
EMSOFT
2011
Springer
12 years 7 months ago
From boolean to quantitative synthesis
Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective a...
Pavol Cerný, Thomas A. Henzinger
CODES
2009
IEEE
14 years 2 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
EMSOFT
2007
Springer
14 years 1 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...