3 search results - page 1 / 1 » An SDRAM-aware router for Networks-on-Chip |
AINA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel analytical model to compute communication latency of broadcast as the most fundamental collective communication operation. The novelty of the model lie...
ERSA
2006
13 years 8 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
DATE
2010
IEEE
14 years 14 days ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...