A method is presented for modeling application performance on parallel computers in terms of the performance of microkernels from the HPC Challenge benchmarks. Specifically, the a...
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
— For most of wireless services with variable rate transmission, both average rate and rate oscillation are important performance metrics. One often needs to decide how much rate...
— The EPC Network is an industry proposal to build a global information architecture for objects carrying RFID tags with Electronic Product Codes (EPC). A so-called Object Naming...