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IPPS
2008
IEEE
14 years 2 months ago
Modeling and predicting application performance on parallel computers using HPC challenge benchmarks
A method is presented for modeling application performance on parallel computers in terms of the performance of microkernels from the HPC Challenge benchmarks. Specifically, the a...
Wayne Pfeiffer, Nicholas J. Wright
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 2 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
CODES
2007
IEEE
14 years 2 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick
ICC
2007
IEEE
129views Communications» more  ICC 2007»
14 years 2 months ago
Time Sharing Policy in Wireless Networks for Variable Rate Transmission
— For most of wireless services with variable rate transmission, both average rate and rate oscillation are important performance metrics. One often needs to decide how much rate...
Xiaolu Zhang, Meixia Tao, Chun Sum Ng
ICC
2007
IEEE
214views Communications» more  ICC 2007»
14 years 2 months ago
Distributed ONS and its Impact on Privacy
— The EPC Network is an industry proposal to build a global information architecture for objects carrying RFID tags with Electronic Product Codes (EPC). A so-called Object Naming...
Benjamin Fabian, Oliver Günther