21 search results - page 4 / 5 » An analysis of on-chip interconnection networks for large-sc... |
ICPPW
1999
IEEE
13 years 11 months ago
1999
IEEE
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
TACO
2010
13 years 5 months ago
2010
CODES
2003
IEEE
14 years 21 days ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
TC
2008
13 years 7 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...