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IEEEPACT
2005
IEEE
14 years 1 months ago
Instruction Based Memory Distance Analysis and its Application
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
DATE
2007
IEEE
128views Hardware» more  DATE 2007»
14 years 1 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
ISPASS
2005
IEEE
14 years 1 months ago
Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering
In this paper we study the properties of a new packet trace compression method based on clustering of TCP flows. With our proposed method, the compression ratio that we achieve i...
Raimir Holanda, Javier Verdú, Jorge Garc&ia...
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 2 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
13 years 5 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis