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ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 3 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISORC
2005
IEEE
14 years 3 months ago
Heterogeneous Adaptive Component-Based Applications with Adaptive.Net
Adaptation to changing environmental conditions is a major challenge for most distributed applications. The service-oriented programming paradigm leads to an increasing number of ...
Andreas Rasche, Marco Puhlmann, Andreas Polze
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 3 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
ANCS
2005
ACM
14 years 3 months ago
Resource mapping and scheduling for heterogeneous network processor systems
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...
Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinh...
SENSYS
2005
ACM
14 years 3 months ago
Intelligent light control using sensor networks
Increasing user comfort and reducing operation costs have always been two primary objectives of building operations and control strategies. Current building control strategies are...
Vipul Singhvi, Andreas Krause, Carlos Guestrin, Ja...