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FPL
2007
Springer
105views Hardware» more  FPL 2007»
14 years 2 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl
ISPASS
2005
IEEE
14 years 2 months ago
Analysis of Network Processing Workloads
Abstract— Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality inside the network. Mode...
Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
CASES
2003
ACM
14 years 1 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
CASES
2005
ACM
13 years 10 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
IBMRD
2011
112views more  IBMRD 2011»
13 years 3 months ago
Sensor Andrew: Large-scale campus-wide sensing and actuation
—We present Sensor Andrew, a multi-disciplinary campus-wide scalable sensor network that is designed to host a wide range of sensor, actuator and low-power applications. The goal...
Anthony Rowe, Mario Berges, Gaurav Bhatia, Ethan G...