112 search results - page 2 / 23 » An efficient FIR filter architecture |
FPL
2008
Springer
13 years 9 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
ISCAS
2003
IEEE
14 years 18 days ago
2003
IEEE
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
ICASSP
2009
IEEE
13 years 11 months ago
2009
IEEE
We provide an analysis of the algorithms necessary for the optimal use of multidimensional signal reconstruction from multichannel acquisition. Firstly, we provide computable cond...
ISCAS
2003
IEEE
14 years 19 days ago
2003
IEEE
— The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals t...
ISCAS
2003
IEEE
14 years 19 days ago
2003
IEEE
Maximum Likelihood estimation theory can be used to develop optimal timing recovery schemes for digital communication systems. Tunable digital interpolation filters are commonly ...