Sciweavers

139 search results - page 10 / 28
» An evolutionary algorithm for reducing integrated-circuit te...
Sort
View
ET
2010
113views more  ET 2010»
13 years 4 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
EMO
2005
Springer
68views Optimization» more  EMO 2005»
14 years 1 months ago
Multi-objective Optimization of Problems with Epistemic Uncertainty
Abstract. Multi-objective evolutionary algorithms (MOEAs) have proven to be a powerful tool for global optimization purposes of deterministic problem functions. Yet, in many real-w...
Philipp Limbourg
SIGSOFT
2007
ACM
14 years 8 months ago
The impact of input domain reduction on search-based test data generation
There has recently been a great deal of interest in search? based test data generation, with many local and global search algorithms being proposed. However, to date, there has be...
Mark Harman, Youssef Hassoun, Kiran Lakhotia, Phil...
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
14 years 19 days ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
14 years 25 days ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...