Sciweavers

2488 search results - page 56 / 498
» An improvement in formal verification
Sort
View
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
FMCAD
2006
Springer
14 years 1 months ago
Post-reboot Equivalence and Compositional Verification of Hardware
We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combin...
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Z...
FMCAD
2004
Springer
14 years 1 months ago
A Partitioning Methodology for BDD-Based Verification
The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this paper we advocate a methodology to handle this probl...
Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain,...
DAC
2006
ACM
14 years 3 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
PERCOM
2010
ACM
13 years 7 months ago
Towards automated verification of autonomous networks: A case study in self-configuration
In autonomic networks, the self-configuration of network entities is one of the most desirable properties. In this paper, we show how formal verification techniques can verify the ...
JaeSeung Song, Tiejun Ma, Peter R. Pietzuch