Sciweavers

399 search results - page 10 / 80
» An integrated performance and power model for superscalar pr...
Sort
View
ISLPED
2003
ACM
86views Hardware» more  ISLPED 2003»
14 years 20 days ago
Exploiting compiler-generated schedules for energy savings in high-performance processors
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
Madhavi Gopal Valluri, Lizy Kurian John, Heather H...
WOSP
2005
ACM
14 years 29 days ago
Modeling the performance of a NAT/firewall network service for the IXP2400
The evolution towards IP-aware access networks creates the possibility (and, indeed, the desirability) of additional network services, like firewalling or NAT, integrated into th...
Tom Verdickt, Wim Van de Meerssche, Koert Vlaeminc...
ISLPED
2006
ACM
100views Hardware» more  ISLPED 2006»
14 years 1 months ago
Selective writeback: exploiting transient values for energy-efficiency and performance
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...
ICS
2010
Tsinghua U.
13 years 6 months ago
Decomposable and responsive power models for multicore processors using performance counters
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
Ramon Bertran, Marc González, Xavier Martor...
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...