257 search results - page 25 / 52 » An optimal algorithm for area minimization of slicing floorp... |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
GECCO
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. A brachistochrone is the path along which a weighted particle falls most quickly from one point to another, and a catenary is the smooth curve connecting two points whose...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
ACCV
2010
Springer
13 years 3 months ago
2010
Springer
We propose a novel variational formulation for generating 3D models of objects from a single view. Based on a few user scribbles in an image, the algorithm automatically extracts t...