257 search results - page 33 / 52 » An optimal algorithm for area minimization of slicing floorp... |
ATS
2001
IEEE
13 years 11 months ago
2001
IEEE
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...