117 search results - page 17 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
ICML
1998
IEEE
14 years 8 months ago
1998
IEEE
This paper introduces a new algorithm, Q2, foroptimizingthe expected output ofamultiinput noisy continuous function. Q2 is designed to need only a few experiments, it avoids stron...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
FPL
1997
Springer
13 years 11 months ago
1997
Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
FOCS
2004
IEEE
13 years 11 months ago
2004
IEEE
We consider a stochastic variant of the NP-hard 0/1 knapsack problem in which item values are deterministic and item sizes are independent random variables with known, arbitrary d...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...