117 search results - page 18 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
DAC
2009
ACM
14 years 2 months ago
2009
ACM
This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximiza...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...