Exploiting STI stress for performance

— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation – has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We perform process simulation of a production 65nm STI technology to generate mobility and delay impact models for STI stress. Based on these models, we are able to perform STI stress-aware delay analysis of critical paths using SPICE. We then present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation to optimize PMOS performance and activelayer fill insertion to optimize NMOS performance. We assess our optimization on small designs implemented with a 65nm production cell library and a standard synthesis, place and rou...

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
• Keywords: Hardware, ICCAD 2007, Production 65nm Sti, STI Stress, STI Stress Impacts