3120 search results - page 22 / 624 » An optimal architecture for a DDC |
EUROGP
2006
Springer
14 years 1 days ago
2006
Springer
Abstract. Theoretical models of Turing complete linear genetic programming (GP) programs suggest the fraction of halting programs is vanishingly small. Convergence results proved f...
ETS
2010
IEEE
13 years 9 months ago
2010
IEEE
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
DAC
1996
ACM
14 years 15 days ago
1996
ACM
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
ESANN
2001
13 years 9 months ago
2001
Neural networks use neurons of the same type in each layer but such architecture cannot lead to data models of optimal complexity and accuracy. Networks with architectures (number ...
DAC
1996
ACM
14 years 15 days ago
1996
ACM
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...