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» An optimal architecture for a DDC
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TPHOL
2000
IEEE
13 years 10 months ago
Verified Optimizations for the Intel IA-64 Architecture
This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The form...
Jim Grundy
CGO
2004
IEEE
13 years 10 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
SCCC
1998
IEEE
13 years 11 months ago
Software Architectural Specification for Optimal Object Distribution
Software architectural design is essential for complex distributed applications. Architectural specifications need to define the key aspects of the application, including its inte...
M. Cecilia Bastarrica, Steven A. Demurjian, Alexan...
TVLSI
2010
13 years 1 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
EUROPAR
2010
Springer
13 years 7 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...